Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complimentary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors, etc.
Each of these semiconductor devices generally include a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode which modulates current between the source and drain regions. In bipolar transistors, an active device generally includes a base, a collector, and an emitter.
A typical semiconductor substrate includes a large number of transistors which are interconnected using one or more layers of metal. FIG. 1 illustrates an exemplary multilevel-interconnect structure for MOS technologies. The interconnect structure illustrated in FIG. 1 includes two metal layers 101 and 102. The first metal layer 101 generally interconnects active portions of the transistors, such as the gate electrode 105 and the source/drain region 104. Each subsequent metal layer, such as second metal layer 102, typically interconnects regions of the previously formed metal layer. Dielectric layers 106 and 107 are provided between conductive structures, such as the metal layers 101 and 102, the gate electrode 105, and the source/drain region 104 in order to isolate these structures from one another. Openings or vias 108 in the dielectric layers 106 and 107 are used to interconnect these structures as desired. A more detailed description of metal layers and the fabrication thereof may be found in S. Wolf, Silicon Processing for the VLSI Era, Vol. 2: Processing Integration, pp. 188-217, 240-260 and 334-337.
One important characteristic of interconnect structures is that capacitance between metal lines is kept to a minimum. It should be appreciated that high capacitance between metal lines can deleteriously affect the speed of a semiconductor device. Two factors affecting such capacitance are the spacing between adjacent metal lines and the material used in the dielectric layers. At present, oxides having dielectric constants ranging from about 3.9 to 4.1 are used to form dielectric layers between metal lines of a semiconductor device.